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Preliminary Technical Data
FEATURES
General HDMITM/DVI transmitter compatible with HDMI v. 1.3, DVI v. 1.0, and HDCP v. 1.2 Internal key storage for HDCP Single 1.8 V power supply Video/audio inputs accept logic levels from 1.8 V to 3.3 V 80-lead LQFP, Pb-free package 64-lead LFCSP, Pb-free package Digital video 165 MHz operation supports all resolutions from 480i to 1080p and UXGA at 60 Hz Programmable two-way color space converter Supports RGB, YCbCr, and DDR Supports ITU656-based embedded syncs Automatic input video format timing detection (CEA-861B) Digital audio Supports standard S/PDIF for stereo LPCM or compressed audio up to 192 kHz 8-channel, uncompressed, LPCM I2S audio up to 192 kHz Special features for easy system design On-chip MPU with I2C(R) master to perform HDCP operations and EDID reading operations 5 V tolerant I2C and HPD I/Os, no extra device needed No audio master clock needed for supporting S/PDIF and I2S On-chip MPU reports HDMI events through interrupts and registers
High Performance HDMI/DVI Transmitter AD9389B
FUNCTIONAL BLOCK DIAGRAM
SCL SDA MCL MDA INT
I2C SLAVE HDCP CORE REGISTER CONFIGURATION LOGIC
INTERRUPT HANDLER
HPD
HDCP-EDID MICROCONTROLLER
CLK VSYNC HSYNC DE D[23:0] VIDEO DATA CAPTURE COLOR SPACE CONVERSION 4:2:2 TO 4:4:4 CONVERSION XOR MASK S/PDIF MCLK I2S[3:0] LRCLK SCLK AUDIO DATA CAPTURE
I2C MASTER
DDCSDA DDCSCL
Tx0-/Tx0+ HDMI Tx CORE Tx1-/Tx1+ Tx2-/Tx2+ TxC-/TxC+
AD9389B
06555-001
Figure 1.
APPLICATIONS
DVD players and recorders Digital set-top boxes A/V receivers Digital cameras and camcorders HDMI repeater/splitter
The AD9389B supports both S/PDIF and 8-channel I2S audio. Its high fidelity, 8-channel I2S can transmit either stereo or 7.1 surround audio at 192 kHz. The S/PDIF can carry stereo LPCM audio or compressed audio, including DTS(R), THX(R), and Dolby(R) Digital. The AD9389B helps reduce system design complexity and cost by incorporating such features as an internal MPU for HDCP operations, an I2C master for EDID reading, a single 1.8 V power supply, and 5 V tolerance on the I2C and hot plug detect pins. Fabricated in an advanced CMOS process, the AD9389B is available in a space-saving, 64-lead LFCSP surface-mount package, and an 80-lead LQFP surface-mount package. All packages are available as Pb-free and are specified from -25C to +85C.
GENERAL DESCRIPTION
The AD9389B is a 165 MHz, high definition multimedia interface (HDMI) v. 1.3 transmitter. It supports HDTV formats up to 1080p, and computer graphic resolutions up to UXGA (1600 x 1200 @ 60 Hz). With the inclusion of HDCP, the AD9389B allows the secure transmission of protected content as specified by the HDCP v. 1.2 protocol.
Rev. PrA
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2007 Analog Devices, Inc. All rights reserved.
AD9389B TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 5 Explanation of Test Levels ........................................................... 5 ESD Caution.................................................................................. 5 Pin Configuration and Function Descriptions............................. 6 Applications....................................................................................... 9
Preliminary Technical Data
Design Resources ..........................................................................9 Document Conventions ...............................................................9 PCB Layout Recommendations.................................................... 10 Power Supply Bypassing ............................................................ 10 Digital Inputs .............................................................................. 10 External Swing Resistor............................................................. 10 Output Signals ............................................................................ 10 Outline Dimensions ....................................................................... 11 Ordering Guide .......................................................................... 12
Rev. PrA | Page 2 of 12
Preliminary Technical Data SPECIFICATIONS
Table 1.
Parameter DIGITAL INPUTS Input Voltage, High (VIH) Input Voltage, Low (VIL) Input Capacitance DIGITAL OUTPUTS Output Voltage, High (VOH) Output Voltage, Low (VOL) THERMAL CHARACTERISTICS Thermal Resistance JC Junction-to-Case JA Junction-to-Ambient Ambient Temperature DC SPECIFICATIONS Input Leakage Current, IIL Input Clamp Voltage Differential High Level Output Voltage Differential Output Short-Circuit Current POWER SUPPLY VDD (All) Supply Voltage VDD Supply Voltage Noise Power-Down Current IAVDD 2 IPVDD2 IDVDD2 Transmitter Supply Current2 Transmitter Total Power AC SPECIFICATIONS CLK Frequency TMDS Output CLK Duty Cycle Worst Case CLK Input Jitter Input Data Setup Time Input Data Hold Time TMDS Differential Swing VSYNC and HSYNC Delay from DE Falling Edge VSYNC and HSYNC Delay to DE Rising Edge DE High Time DE Low Time Differential Output Swing Low-to-High Transition Time High-to-Low Transition Time
Rev. PrA | Page 3 of 12
AD9389B
Conditions
Temp Full Full 25C Full Full
Test Level 1 VI VI V VI VI
Min 1.4
Typ
Max 3.5 0.7
Unit V V pF V V
3 VDD - 0.1 0.4
Full 25C 25C 25C
V V V VI V V V IV
-25 -10
15.2 59 +25
+85 +10
C/W C/W C A V V V A
-16 mA +16 mA
-0.8 +0.8 AVCC 10
With active video applied, 165 MHz, typical random pattern With active video applied, 165 MHz, typical random pattern With active video applied, 165 MHz, typical random pattern With active video applied, 165 MHz, typical random pattern With active video applied, 165 MHz, typical random pattern
Full Full 25C 25C 25C 25C 25C Full 25C 25C Full Full Full
IV V IV IV IV IV IV VI IV IV IV IV IV VI VI VI
1.71
1.8 9 TBD TBD TBD TBD TBD
1.89 50
V mV p-p mA
mA mW 80 52 2 MHz % ns ns ns mV UI 3 UI 8191 UI UI ps ps
13.5 48 1 1 800
1000 1 1
1200
25C 25C 25C 25C
VI VI VII VII 75 75
138 490 490
AD9389B
Parameter AUDIO AC TIMING Sample Rate I2S Cycle Time I2S Setup Time I2S Hold Time Audio Pipeline Delay
1 2
Preliminary Technical Data
Conditions I2S and S/PDIF Temp Full 25C 25C 25C 25C Test Level 1 IV IV IV IV IV Min 32 15 0 75 Typ Max 192 1 Unit kHz UI ns ns s
See Explanation of Test Levels section. Using low output drive strength. 3 UI = unit interval.
Rev. PrA | Page 4 of 12
Preliminary Technical Data ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Digital Inputs Digital Output Current Operating Temperature Range Storage Temperature Range Maximum Junction Temperature Maximum Case Temperature Rating 5 V to 0.0 V 20 mA -40C to +85C -65C to +150C 150C 150C
AD9389B
EXPLANATION OF TEST LEVELS
I. II. III. IV. V. VI. VII. 100% production tested. 100% production tested at 25C and sample tested at specified temperatures. Sample tested only. Parameter is guaranteed by design and characterization testing. Parameter is a typical value only. 100% production tested at 25C; guaranteed by design and characterization testing. Limits defined by HDMI specification; guaranteed by design and characterization testing.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
Rev. PrA | Page 5 of 12
AD9389B PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
DVDD DVDD DVDD
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
Preliminary Technical Data
DVDD
GND
GND
D10
D11
D12
D13
D14
D1
D2
D3
D4
D5
D6
D7
D8
D9
DVDD 1 D0 DE HSYNC VSYNC
2 3 4 5
PIN 1 INDICATOR
60 59 58 57 56 55 54 53
GND GND D15 D16 D17 D18 D19 D20 D21 D22 D23 MCL MDA SDA SCL DDCSDA DDCSCL GND GND AVDD
CLK 6 S/PDIF 7 MCLK 8 I2S0
9
AD9389B
TOP VIEW (Not to Scale)
52 51 50 49 48 47 46 45 44 43 42 41
I2S1 10 I2S2 11 I2S3 12 SCLK 13 LRCLK 14 GND 15 PVDD 16 GND 17 GND 18 PVDD 19 PVDD 20
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
EXT_SWG
GND
GND
GND
GND
Tx0+
Tx1+
PVDD
TxC+
TxC-
PD/A0
AVDD
AVDD
AVDD
Tx2+
HPD
Tx0-
Tx1-
Tx2-
INT
Figure 2. 80-Lead LQFP Pin Configuration (Top View)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
DGND D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 DVDD
DVDD D0 DE HSYNC VSYNC CLK S/PDIF MCLK I2S0 I2S1 I2S2 I2S3 SCLK LRCLK PVDD PVDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
PIN 1 INDICATOR
+
AD9389B
TOP VIEW (Not to Scale)
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
DVDD D15 D16 D17 D18 D19 D20 D21 D22 D23 MCL MDA SDA SCL DDCSDA DDCSCL
PVDD EXT_SWG AVDD HPD TxC- TxC+ AVDD Tx0- Tx0+ PD/A0 Tx1- Tx1+ AVDD Tx2- Tx2+ INT
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
NOTES 1. GND PADDLE ON BOTTOM OF PACKAGE.
Figure 3. 64-Lead LFCSP Pin Configuration (Top View)
Rev. PrA | Page 6 of 12
06555-003
06555-002
Preliminary Technical Data
Table 3. Pin Function Descriptions
LFCSP 2, 39 to 47, 50 to 63 6 3 4 5 18 20 7 Pin No. LQFP 2, 50 to 58, 65 to 78 6 3 4 5 23 25 7 Mnemonic D[23:0] CLK DE HSYNC VSYNC EXT_SWG HPD S/PDIF Type 1 I I I I I I I I
AD9389B
8
8
MCLK
I
9 to 12 13 14 262
9 to 12 13 14 332
I2S[3:0] SCLK LRCLK PD/A0
I I I I
21, 22 30, 31 27, 28 24, 25 32 19, 23, 29 1, 48, 49 15 to 17
27, 28 37, 38 34, 35 30, 31 40 24, 29, 36, 41 1, 61 to 64 16, 19 to 21
TxC-/TxC+ Tx2-/Tx2+ Tx1-/Tx1+ Tx0-/Tx0+ INT AVDD DVDD PVDD
O O O O O P P P
64, paddle on bottom side 36 35 37 38
15, 17, 18, 22, 26, 32, 39, 42, 43, 59, 60, 79, 80 47 46 48 49
GND
P
SDA SCL MDA MCL
C2 C2 C2 C2
Description Video Data Input. Digital input in RGB or YCbCr format. Supports CMOS logic levels from 1.8 V to 3.3 V. Video Clock Input. Supports CMOS logic levels from 1.8 V to 3.3 V. Data Enable Bit for Digital Video. Supports CMOS logic levels from 1.8 V to 3.3 V. Horizontal Sync Input. Supports CMOS logic levels from 1.8 V to 3.3 V. Vertical Sync Input. Supports CMOS logic levels from 1.8 V to 3.3 V. Sets internal reference currents. Place an 887 resistor (1% tolerance) between this pin and ground. Hot Plug Detect Signal. This indicates to the interface whether the receiver is connected. 1.8 V to 5.0 V CMOS logic level. S/PDIF (Sony/Philips Digital Interface) Audio Input. This is the audio input from a Sony/Philips digital interface. Supports CMOS logic levels from 1.8 V to 3.3 V. Audio Reference Clock. 128 x N x fS with N = 1, 2, 3, or 4. Set to 128 x sampling frequency (fS), 256 x fS, 384 x fS, or 512 x fS. Supports 1.8 V to 3.3 V CMOS logic level. I2S Audio Data Inputs. These represent the eight channels of audio (two per input) available through I2S. Supports CMOS logic levels from 1.8 V to 3.3 V. I2S Audio Clock. Supports CMOS logic levels from 1.8 V to 3.3 V. Left/Right Channel Selection. Supports CMOS logic levels from 1.8 V to 3.3 V. Power-Down Control and I2C Address Selection. The I2C address and the PD polarity are set by the PD/A0 pin state when the supplies are applied to the AD9389B. Supports 1.8 V to 3.3 V CMOS logic level. Differential Clock Output. Differential clock output at pixel clock rate; TMDS logic level. Differential Output Channel 2. Differential output of the red data at 10x the pixel clock rate; TMDS logic level. Differential Output Channel 1. Differential output of the green data at 10x the pixel clock rate; TMDS logic level. Differential Output Channel 0. Differential output of the blue data at 10x the pixel clock rate; TMDS logic level. Interrupt. Open drain. A 2 k pull-up resistor to the microcontroller I/O supply is recommended. 1.8 V Power Supply for TMDS Outputs. 1.8 V Power Supply for Digital and I/O Power Supply. These pins supply power to the digital logic and I/Os. They should be filtered and as quiet as possible. 1.8 V PLL Power Supply. The most sensitive portion of the AD9389B is the clock generation circuitry. These pins provide power to the clock PLL. The designer should provide quiet, noise-free power to these pins. Ground. The ground return for all circuitry on-chip. It is recommended that the AD9389B be assembled on a single, solid ground plane with careful attention given to ground current paths. Serial Port Data I/O. This pin serves as the serial port data I/O slave for register access. Supports CMOS logic levels from 1.8 V to 3.3 V. Serial Port Data Clock. This pin serves as the serial port data clock slave for register access. Supports CMOS logic levels from 1.8 V to 3.3 V. Serial Port Data I/O Master to HDCP Key EEPROM. Supports CMOS logic levels from 1.8 V to 3.3 V. Serial Port Data Clock Master to HDCP Key EEPROM. Supports CMOS logic levels from 1.8 V to 3.3 V.
Rev. PrA | Page 7 of 12
AD9389B
LFCSP 34 33
1 2
Preliminary Technical Data
Mnemonic DDCSDA DDCSCL Type 1 C2 C2 Description Serial Port Data I/O to Receiver. This pin serves as the master to the DDC bus. Supports a 5 V CMOS logic level. Serial Port Data Clock to Receiver. This pin serves as the master clock for the DDC bus. Supports a 5 V CMOS logic level.
Pin No. LQFP 45 44
I = input, O = output, P = power supply, C = control. For a full description of the 2-wire serial interface and its functionality, obtain documentation by contacting NDA from flatpanel_apps@analog.com.
Rev. PrA | Page 8 of 12
Preliminary Technical Data APPLICATIONS
DESIGN RESOURCES
Analog Devices, Inc. evaluation kits, reference design schematics, and other support documentation are available under the nondisclosure agreement (NDA) from flatpanel_apps@analog.com. Other resources include: EIA/CEA-861B which describes audio and video infoframes as well as the E-EDID structure for HDMI. It is available from Consumer Electronics Association (CEA). The HDMI v. 1.3, a defining document for HDMI Version 1.3, and the HDMI Compliance Test Specification Version 1.3 are available from HDMI Licensing, LLC. The HDCP v. 1.2 is the defining document for HDCP Version 1.2 available from Digital Content Protection, LLC.
AD9389B
DOCUMENT CONVENTIONS
In this data sheet, data is represented using the conventions described in Table 4. Table 4. Document Conventions
Data Type 0xNN 0bNN NN Bit Format Hexadecimal (Base-16) numbers are represented using the C language notation, preceded by 0x. Binary (Base-2) numbers are represented using the C language notation, preceded by 0b. Decimal (Base-10) numbers are represented using no additional prefixes or suffixes. Bits are numbered in little endian format, that is, the least significant bit of a byte or word is referred to as Bit 0.
Rev. PrA | Page 9 of 12
AD9389B PCB LAYOUT RECOMMENDATIONS
The AD9389B is a high precision, high speed analog device. As such, to obtain the maximum performance from the part, it is important to have a well laid out board.
Preliminary Technical Data
Other Input Signals
The HPD must be connected to the HDMI connector. A 10 k pull-down resistor to ground is also recommended. The PD/A0 input pin can be connected to GND or supply (through a resistor or a control signal). The device address and power-down polarity are set by the state of the PD/A0 pin when the AD9389B supplies are applied/enabled. For example, if the PD/A0 pin is low (when the supplies are turned on), then the device address is 0x72 and the power-down is active high. If the PD/A0 pin is high (when the supplies are turned on), the device address is 0x7A and the power-down is active low. The SCL and SDA pins should be connected to the I2C master. A pull-up resistor of 2 k to 1.8 V or 3.3 V is recommended.
POWER SUPPLY BYPASSING
It is recommended to bypass each power supply pin with a 0.1 F capacitor. The exception is when two or more supply pins are adjacent to each other. For these groupings of powers/grounds, it is necessary to have only one bypass capacitor. The fundamental idea is to have a bypass capacitor within about 0.5 cm of each power pin. Also, avoid placing the capacitor on the opposite side of the PC board from the AD9389B, as that interposes resistive vias in the path. The bypass capacitors should be physically located between the power plane and the power pin. Current should flow from the power plane to the capacitor to the power pin. Do not make a power connection between the capacitor and the power pin. Placing a via underneath the capacitor pads, down to the power plane, is generally the best approach. It is particularly important to maintain low noise and good stability of PVDD (the PLL supply). Abrupt changes in PVDD can result in similarly abrupt changes in sampling clock phase and frequency. This can be avoided by careful attention to regulation, filtering, and bypassing. It is best practice to provide separate regulated supplies for each of the analog circuitry groups (AVDD and PVDD). It is also recommended to use a single ground plane for the entire board. Experience has repeatedly shown that the noise performance is the same or better with a single ground plane. Using multiple ground planes can be detrimental because each separate ground plane is smaller, and long ground loops can result.
EXTERNAL SWING RESISTOR
The external swing resistor must be connected directly to the EXT_SWG pin and ground. The external swing resistor must have a value of 887 (1% tolerance). Avoid running any high speed ac or noisy signals next to, or close to, the EXT_SWG pin.
OUTPUT SIGNALS
TMDS Output Signals
The AD9389B has three TMDS data channels (0, 1, and 2) that output signals up to 800 MHz as well as the TMDS output data clock. To minimize the channel-to-channel skew, make the trace length of these signals the same. Additionally, these traces need to have a 50 characteristic impedance and need to be routed as 100 differential pairs. Best practice recommends routing these lines on the top PCB layer to avoid the use of vias.
Other Output Signals (non TMDS) DDCSCL and DDCSDA
The DDCSCL and DDCSDA outputs need to have a minimum amount of capacitance loading to ensure the best signal integrity. The DDCSCL and DDCSDA capacitance loading must be less than 50 pF to meet the HDMI compliance specification. The DDCSCL and DDCSDA must be connected to the HDMI connector and a pull-up resistor to 5 V is required. The pull-up resistor must have a value between 1.5 k and 2 k.
DIGITAL INPUTS
Video and Audio Data Input Signals
The digital inputs on the AD9389B are designed to work with signals ranging from 1.8 V to 3.3 V logic level. Therefore, no extra components need to be added when using 3.3 V logic. Any noise that gets onto the clock input (labeled CLK) trace adds jitter to the system. Therefore, minimize the video clock input (Pin 6: CLK) trace length and do not run any digital or other high frequency traces near it. Make sure to match the length of the input data signals to optimize data capture, especially for high frequency modes such as 1080p, UXGA, and double data rate input formats.
INT Pin
The INT pin is an output that should be connected to the microcontroller of the system. A pull-up resistor to 1.8 V or 3.3 V is required for proper operation--the recommended value is 2 k.
MCL and MDA
The MCL and MDA outputs should be connected to the EEPROM containing the HDCP key (if HDCP is implemented). Pull-up resistors of 2 k are recommended.
Rev. PrA | Page 10 of 12
Preliminary Technical Data OUTLINE DIMENSIONS
0.75 0.60 0.45 1.60 MAX
80 1 PIN 1
AD9389B
16.20 16.00 SQ 15.80
61 60
TOP VIEW (PINS DOWN)
14.20 14.00 SQ 13.80
1.45 1.40 1.35
0.15 0.05
SEATING PLANE
0.20 0.09 7 3.5 0 0.10 MAX COPLANARITY
20 21 40
41
VIEW A
VIEW A
ROTATED 90 CCW
0.65 BSC LEAD PITCH
0.38 0.32 0.22
COMPLIANT TO JEDEC STANDARDS MS-026-BEC
Figure 4. 80-Lead Low Profile Quad Flat Package [LQFP] (ST-80-2) Dimensions shown in millimeters
0.30 0.25 0.18
64 1
9.00 BSC SQ
0.60 MAX 0.60 MAX
49 48
PIN 1 INDICATOR
PIN 1 INDICATOR
+
TOP VIEW
8.75 BSC SQ
EXPOSED PAD**
(BOTTO M VIEW)
4.85 4.70 SQ* 4.55
0.45 0.40 0.35
33 32
17
16
1.00 0.85 0.80
12 MAX
0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.50 BSC
7.50 REF
SEATING PLANE
0.20 REF
64 LFCSP (LEAD FRAME CHIP SCALE PACKAGE) * COMPLIANT TO JEDEC STANDARDS MO-220-VMMD EXCEPT FOR EXPOSED PAD DIMENSION **Note: PAD is CONNECTED to GND
DIMENSIONS in Millimeters
Figure 5. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 9 mm x 9 mm Body, Very Thin Quad (CP-64-1) Dimensions shown in millimeters
Rev. PrA | Page 11 of 12
AD9389B
ORDERING GUIDE
Model AD9389BBCPZ-801 AD9389BBCPZ-1651 AD9389BBSTZ-801 AD9389BBSTZ-1651 AD9389B/PCB
1
Preliminary Technical Data
Temperature Range -25C to +85C -25C to +85C -25C to +85C -25C to +85C Package Description 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 80-Lead Low Profile Quad Flat Package [LQFP] 80-Lead Low Profile Quad Flat Package [LQFP] Evaluation Board Package Option CP-64-1 CP-64-1 ST-80-2 ST-80-2
Z = RoHS Compliant Part.
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
(c)2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR06555-0-3/07(PrA)
Rev. PrA | Page 12 of 12

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